The present invention relates to programmable logic devices, and more particularly to techniques for providing high speed programming and verification of device array programming data and logic paths.
Digital systems such as computers typically are fabricated from many logic and memory integrated circuits or chips. A goal of microelectronic integration is to fit the memory and logic circuits of a system onto the fewest possible integrated circuits, to minimize the cost and increase the system speed and reliability.
Useful memories are relatively easy to define, but logic circuits present a problem to integrated circuit manufacturers, who cannot afford to make logic integrated circuits which are perfectly tailored to the specific needs of every customer. Instead, generally purpose VLSI circuits are defined which can serve as many roles as possible. For example, the microprocessor allows logic functions to be expressed in software, and together with memory units and standard peripheral is capable of consolidating much of the logic in a digital system. However, random logic circuits are still required to tie these elements of the the system together.
Several schemes are used to implement these random Logic circuits. One solution is standard logic, such as transistor-transistor logic (TTL). TTL integrated circuits are versatile because they integrate only a relatively small number of commonly used logic functions. The drawback is number of commonly used logic functions. The drawback is that large numbers of TTL integrated circuits are typically required for a specific application, increasing the consumption of power and board space, and driving up the overall cost of the digital system.
Other alternatives include fully custom logic integrated circuits and semi-custom logic integrated circuits, such as gate arrays. Custom logic circuits, precisely tailored to the needs of a specific application, allow the implementation of specific circuit architectures, dramatically reducing the number of parts required for a system. However, custom logic devices require significantly greater engineering time and effort, which increases the cost to develop these circuits and may also delay the production of the end system.
Semi-custom gate arrays are less expensive to develop and offer faster turnaround because the circuits are typically identically except for a few final-stage steps, which are customized according to the system design specifically. However, semi-custom gate arrays are less dense, so that it takes more gate array circuits than custom circuits to implement a given amount of random logic.
Between the extremes of general purpose devices on the one hand and custom and semi-custom gate arrays on the other, are programmable logic devices (PLDs). PLDs provide a flexible architecture, user-programmed through on-chip fuses or switches, to perform specific functions for a give application. PLDs can be purchased "off the shelf" like standard logic gates, but can be custom tailored like gate arrays in a matter of minutes.
To use PLDs, system designers draft equations describing how the hardware is to perform, and enter the equations into a PLD programming machine. The unprogrammed PLDs are inserted into the machine, which interprets the equations and provides appropriate signals to the device to blow the the PLD which will perform the desired logic function in the user's system. The PLD typically includes hundreds of thousands of the fuses or switches, arranged in a matrix to facilitate their manufacture and programming.
Programmable logic devices ("PLDs") have historically been programmed one bit at a time in a serial fashion. The main reason for this approach is that the PLDs have predominantly been implemented in a bipolar technology which requires high currents (on the order of 30 mA) to program bits of data. Programming many bits in parallel would produce destructive power dissipation.
Recently, PLDs based on erasable-programmable-read-only memory cells (EPROMs) fabricated with CMOS (complimentary-metal-oxide-semiconductor) technology have been introduced. Such devices employ floating gate transistors as the PLD switches, which are programmed by hot electron effects. The EPROM cells are erased by exposure to ultraviolet light, which is quite time consuming. Another disadvantage of EPROM-based PLDs is the relatively high expense of the device packaging, which is driven up by the high cost of the quartz window provided to pass the ultraviolet light.
At least one EPROM-based PLD on the market today is apparently adapted for "byte" programming wherein eight programmable connections are programmed simultaneously. These devices would appear to still dissipate too much power to successfully program a large number of cells of parallel, since each bit requires from 2 to 10 mA of current for programming. The data is programmed by selecting a row address and a column address, and presenting the eight bits of data to be programmed to the device outputs. A reasonable upper limit on successful parallel programming is currently eight bits for this technology.
The time needed to program the PLD is an important consideration. Bipolar PLDs will obtain typical programming times in the range of 0.5 to 5 seconds for a 1K by 8 bit array. EPROM-based PLDs will obtain typical programming times in the range of about 40 to 100 seconds for a 1K by 8 bit array if "single bit" programming is employed. If "byte" programming is employed, then the programming time is reduced to a typical range of about 5 to 15 seconds.
Another problem of known PLDs relates to verification of output logic paths. The typical PLD comprises a programmable array, followed by sense amplifiers, logic gates and output drivers eventually arriving at the device output. (The exact configuration will depend on the particular device.) A typical PLD output structure comprises an array, sense amplifers, an OR gate, and an output register, coupled to the device output pin. The output data at the output pin does not have a one-to-one correlation to data on a specific product term or column of the array, as is the case for a memory. The typical way to determine if the output devices are working properly is to program the array with a bit pattern and test to see if the output logic is working. Because bipolar fuses are destructively programmed, it is not possible to verify operation of all the output devices. It is also known to provide a test input to an OR gate to test its functionality, but this does not verify operation of the sense amplifiers or other OR gate inputs.
It is known to provide the capability of high speed fuse verification, but insofar as applicant is aware, the known techniques employ separate verification sense amplifers, thereby providing a somewhat different verification signal path from the normal user signal path through the normal use sense amplifier. Thus, the known techniques do not verify operation of the normal use sense amplifers, which may be inoperative due to manufacturing defects. Moreover, the use of separate sense amplifiers, with possibly different sense thresholds can lead to different results, i.e., the fuse-verify sense amplifier may sense an open cell, but the normal logic sense amplifier may sense a closed cell.
It is therefore a principle object of the invention to provide a programmable logic device which may be programmed at very high speed.
Another object is to provide a PLD with the capability of high speed verification of the programmed data using the normal sense amplifers.
A further object is to provide a PLD with the capability of verifying the operation of the device output logic devices.
Another object is to provide an improved PLD which requires lower power consumption and is reprogrammable by the manufacturer and the user.
Another object of the invention is to provide a PLD employing electrically erasable memory cells to store the programmed data.